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6 Example III: Constraining a Circuit

In this section, we will go through the synthesis process of a small design step by step and explore different constraints. Try

to understand all of the steps – for further explanations and more details please refer to the Synopsys Online Documentation

(SOLD), which can be launched using the following UNIX shell command:

sh > synopsys-2014.09 sold

For the following steps we will use an example circuit that contains sequential cells as well as combinational parts. This

circuit could be part of the ALU inside the datapath of a processor, for doing some special kind of “multiply and accumulate”

operation. The sourcecode of the design can be found in the ﬁle ./sourcecode/datapath.vhd.

Have a look at the sourcecode in order to understand the design. If you did not yet start the cockpit, step into the root

directory of this exercise and start it:

sh > cd u3

sh > icdesign umcL65 &

Make sure that the DC Shell-xg-t option is selected and click SYNOPSYS in order to launch the DC Shell.

6.1 Initial Design

We will now guide you through the synthesis steps. You should already be familiar with many of the SYNOPSYS DESIGN

COMPILER commands mentioned throughout this example.

Note: Keep in mind what you have learned during the previous example of this exercise, i.e., that it might be a good

idea to build a script for all of your synthesis steps.

Analyze and elaborate the design:

dcs > analyze -format vhdl ../sourcecode/datapath.vhd

dcs > elaborate datapath

Now let’s just compile and see what will be generated by the SYNOPSYS DESIGN COMPILER.

dcs > compile

Notice that the compilation process reports some information about the design. More detailed reports can be obtained by

means of SYNOPSYS DESIGN COMPILER’s report commands. As already mentioned during Example II, these commands

can be used to extract and analyze the performance ﬁgures of a synthesized netlist. Answer each of the following questions

by using the appropriate report command.

Student Task 4:

• What is the total cell area? A =

• What is the critical path length? t

• What would be the maximum operating frequency

? f

max

• How many different references are used in this design? N

ref

• A single two-input ND2 gate occupies an area of 1 GE (Gate Equivalent). In the present technology (i.e., UMC

65 nm) the area required for a ND2 is equal to 1.44 µm

. Determine the complexity of our current design in

gate equivalents. Area

Assume that registers are placed at the input and outputs with ideal timing parameters

For more information, check the corresponding entry in the DZ-Wiki under http://eda.ee.ethz.ch/index.php/UmcL65,

as well as the standard cell library application note and handbook available in your exercise directory under ./docs/\

stdcell low vt b03 appnote.pdf and ./docs/stdcel l low vt b03 databook.pdf, respectively.

Note: Remember that most of your answers should have a measuring unit, otherwise they are meaningless.

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