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9 Commonly used Synopsys Design Compiler Commands

Table 4: A short cheatsheet for the Synopsys Design Compiler.

Command Description

User Interface Commands

help List available commands

man Displays reference manual pages of a command

history Lists previously entered commands

sh Execute shell commands

source Read a ﬁle and evaluate it as a Tcl script

gui start Starts the application GUI

gui stop Stops the application GUI

exit

Design Database Commands

analyze Reads and analyzes the HDL ﬁles and stores the intermediate format in the speciﬁed design

library

elaborate Builds a design from the intermediate format (maps to gtech lib)

remove design Removes the designs or libraries from memory

check design Checks the current design for consistency

find Finds a design or library object

list instances Lists the instances in the current design or current instance

write Writes a design netlist to a ﬁle

current design Sets the working design

link Resolves design references (shows libraries and if there are black boxes)

write script Writes shell commands to save the current settings

Attribute and Constraint Commands

set attribute Sets an attribute to an object (cell, clock...)

create clock Creates a clock object and deﬁnes its waveform

set max delay Speciﬁes a maximum delay target for paths in the current design

set driving cell Deﬁne the cell drives of the speciﬁed ports

set drive Deﬁne the driver’s strength to a driver of the speciﬁed ports

set load Sets the load attribute of the speciﬁed ports

load of Returns the capacitance of the speciﬁed library cell pin

set input delay Sets input delay on ports relative to a clock signal

set output delay Sets output delay on ports relative to a clock signal

all inputs Returns the input and inout ports of the current design

all outputs Returns the output and inout ports of the current design

all registers Returns the sequential cells of the current design

Optimization Commands

compile Performs the synthesis and optimization on the current design

compile ultra Performs a high-eﬀort compile on the current design

set ungroup Sets the attribute that blocks are to be ungrouped during compile

set flatten Sets/unset the ﬂatten attribute to enable or disable the ﬂattening optimization step during

compile

set map only Sets the attribute so that they are excluded from logiclevel optimization during compile

Report and Analysis Commands

report timing Displays timing information about a design

report area Displays area information for the current design or instance

report hierarchy Displays the reference hierarchy of the current instance or design

report design Displays attributes of the current design

report net fanout Displays net fanout or buﬀer tree information for the current design

check timing Checks for possible timing problems in the current design

You have reached the end of Exercise 3. Discuss your results with an assistant.

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